1. Field
This patent specification relates generally to a semiconductor integrated circuit device, and to a method for fabricating such device, and more specifically to a placement and routing method of the building-block type for use in deep-submicron processes for reducing the wiring delay and facilitating tapering control of connecting wires, and a device fabricated by this layout method.
2. Discussion of the Background
In the processes for designing a large-scale integrated semiconductor circuit device, respective blocks of the device are generally designed in parallel to complement device characteristics with one another.
During the designing the large-scale device, the building-block type of method is utilized, in which the circuit of the device is divided into a plurality of blocks and each of the blocks is thus designed at the same time. The overall design of the device is then carried out by integrating these constituent blocks.
FIG. 1 includes a flow chart illustrating a basic process flow in the building-block method for designing a block layout. The building-block method is divided broadly into two processes; (1) The process of forming a block layout and (2) interconnecting the plural block. Namely, a block netlist is first tabulated according to several lists on the circuits in the block, and automatic routing for the block layout is then carried out. Subsequently, a TOP netlist, list for the first layer components, is tabulated and connections between the plural blocks are carried out.
In contrast to the building-block method, an alternative or flat layout designing method is illustrated in FIG. 2, in which a TOP netlist is tabulated and the connections by automatic routing are carried out.
The designing in the flat layout method is therefore carried out entirely in a planar fashion as described above. Since the layout in the building-block method is carried out in the unit of device function, in contrast, circuits of each functional component can be designed without undue spread of each layout area, which is more advantageous to secure the characteristics of each block.
FIG. 3 is a block diagram illustrating a block layout formed by the previous building-block method having blocks and interconnections therebetween. The interconnections by this method are designed as shown in FIG. 3, in which block layout is first made for each of the blocks A and B, then connections are carried out between the thus prepared blocks.
In the building-block method, each of the blocks 100 is provided with a plurality of relay terminals 101 in the edge portion to be utilized for relaying signals. In addition, among the plurality of the relay terminals shown in FIG. 3, the terminals A1 and B1 of the blocks A and B, respectively, are interconnected in routing process step.
In addition, there also provided inside the block 100 are terminals 102, from which another connection is also made with the above mentioned relay terminal 101. For example, with the relay terminal A1 (FIG. 3), a wire is connected which is originated from an internal terminal A1xe2x80x2 and extends to a relay terminal in the edge portion. In a similar manner, another wiring from internal terminal 102 (B1xe2x80x2) is also provided to a relay terminal 101 (D1xe2x80x2).
In those pervious building-block method, however, several drawbacks are encountered are such as, for example, unnecessarily long wiring for the interconnection among the plurality of integrated circuit blocks or the cells within the same block.
These drawbacks are exemplified in FIG. 3, in that the wiring is relatively long within the block layout connecting from an inside terminal to a relay terminal in the edge portion, that is caused by bypassing other connections within the block (A1-A1xe2x80x2 or B1-B1xe2x80x2 of FIG. 3).
In addition, since the terminals for the inter-block connections are rather concentrated in the edge portion of the block, the wire length for the inter-block connection may become unduly large as exemplified by the connection A1-B1 of FIG. 3 This may be contrasted by a shorter connection C1-D1 illustrating a more suitable case of the interconnection.
The difference in the above noted wiring length may give rise to several effects such as, for example, skews induced by clock signals having an opposing phase, which may cause a circuit malfunction in the block.
The long wiring tends to result in another disadvantage such as a considerable wiring delay caused by coupling or crosstalk. In addition, the long wiring is unfavorable not only in cost (from chip area consideration) but also in reduced device characteristics.
As a method for achieving high speed circuitry with the long wiring, the wiring may be formed with wider metal to reduce resistance. This is exemplified by the wiring A1-B1 of FIG. 6 formed with the upper 4th metal across the block area, that is more advantageous than the wiring formed in the bottom layer because of its shorter distance.
However, the thus formed wiring still has an undue length resulted from the connection with the terminals placed in the edge portion (A1-A1xe2x80x2 or B1-B1xe2x80x2 of FIG. 6) generally formed in the previous wiring method.
Also in the above described method for achieving high speed circuitry with the long wiring having a wider metal, the method of tapering is generally adapted for forming the connection from the wiring to a cell terminal in the block (which will be detailed later in reference to FIG. 27) to reduce the resistance as much as possible. This is achieved with a wiring changing its width in steps.
However, this method is not completely satisfying since it may cause an undue wiring delay resulting from the stepwise change in the width or additional wiring possibly needed for detouring connection.
In addition, a buffer is placed in the middle of a long connecting wire, and generally in the channel region between the blocks. When the buffer is formed distant from a terminal, the wiring which interconnects the buffer and the terminal and which is to be buffered, may become unduly long (FIG. 21).
Further, the long wiring may result the antenna effect which is known as a mode of destroying a gate (gate oxide), caused by the electric charge accumulated in a connecting wire during manufacturing process when the gate is connected to a conductor (or connecting wire) having a area larger than that of the gate.
In order to alleviate this failure mode, several measures are taken in previous methods such as incorporating an input protection diode in each standard cell, or carrying out the designing so as to meet the antenna rule by means of software control with autoplacement and routing tool.
These measures are not completely satisfying, since the size of the standard cell increases when the input protection diode is incorporated, which may increase the device cost. Also, in the above mentioned method of autoplacement and routing tool, the control becomes more difficult in automatic switching steps from one wiring layer to another during the designing.
Accordingly, it is an object of the present disclosure to provide improved semiconductor integrated circuit device and method for fabricating such device, having most, if not all, of the advantages and features of similar employed devices and methods, while eliminating many of their disadvantages.
It is another object of the present disclosure to provide a semiconductor integrated circuit device fabricated with reduced size and wire connections, to thereby be able to alleviate wiring delay.
It is still another object the present disclosure to provide an improved placement and routing method of the building-block type for use in deep-submicron processes for fabricating the semiconductor device.
The following brief description is a synopsis of only selected features and attributes of the present disclosure. A more complete description thereof is found below in the section entitled xe2x80x9cDescription of Preferred Embodimentsxe2x80x9d
The semiconductor integrated circuit device includes at least a plurality of integrated circuit blocks to be interconnected by wiring. The integrated circuit blocks are each provided with a plurality of terminal cells each including a terminal target metal that is different from, and formed in a layer higher at least by one layer than, ordinary target metals originally included in a block netlist. In addition, the terminal target metal is formed of an upper metal for use in interconnecting the integrated circuit blocks.
According to another aspect, the semiconductor integrated circuit device alternatively includes at least a plurality of integrated circuit blocks to be interconnected by wiring, a plurality of block terminals provided in circumferential edge portions of a block layout, and a terminal cell provided inside of the block layout for use in connecting with a terminal in the integrated circuit block, in which the at least one terminal cell includes a terminal target metal that is different from, and formed in a layer higher at least by one layer than, ordinary target metals originally included in a block netlist. In addition, the interconnection among the integrated circuit blocks is carried out by way of the block terminals provided in circumferential edge portions of a block layout and the terminal targets of the terminal cell.
According to still another aspect, the semiconductor integrated circuit device may alternatively include a plurality of integrated circuit blocks to be interconnected by wiring, a plurality of block terminals provided in circumferential edge portions of a block layout, and a plurality of terminal cells each provided inside of the block layout for use in connecting with a terminal in the integrated circuit block, in which at least one of the terminal cells each includes a terminal target metal that is different from, and formed in a layer higher at least by one layer than, ordinary target metals originally included in the block netlist.
In addition, a metal provided as a target by the terminal cells is formed including a plurality of cells which have a structure of any one of single layered and multi-layered and which include the target metal different from each other. Further, the interconnection among the integrated circuit blocks is carried out by preferentially placing the terminal cell according to the direction of wiring connection with the integrated circuit block and to the preferential wiring direction and by interconnecting the integrated circuit blocks by way of the block terminals provided in circumferential edge portions on the block layout and the terminal targets of the terminal cells.
In these semiconductor integrated circuit devices, at least one of the terminal cells may each be formed to additionally include a capacitor, a buffer, a diode, a power and ground strap, or a cell function device. In addition, at least one of the terminal cells may each be formed independent of any one of input and output terminals of the buffer device to be connected with the terminal for interconnecting the integrated circuit blocks, having the width larger than the pitch, and of the height larger than that, of terminals of a plurality of the cell function devices.
According to another aspect, a method is disclosed for placement and routing of the semiconductor integrated circuit devices, including the steps of tabulating a block netlist, forming a plurality of terminal cells each including a terminal target metal that is different from, and formed in a layer higher at least by one layer than, ordinary target metals originally included in the block netlist, adding the terminal cell to an input/output terminal included in the block netlist, to be subsequently adopted newly as a block terminal, obtaining the coordinates of the terminal cells from a layout obtained through autoplacement and routing steps, forming a layout including only the terminal cells, providing block terminals in circumferential edge portions on the block layout by laying out the layout thereonto, forming a block layout for a terminal target provided in the integrated circuit block with each of the terminal cells as a termination, and interconnecting the integrated circuit blocks by way of the block terminals provided in circumferential edge portions on a block layout and the terminal targets of the terminal cells.
The present disclosure and features and advantages thereof will be more readily apparent from the following detailed description and appended claims when taken with drawings.